Tanner EDA HiPer Silicon v15 Design Suite

Tanner EDA announced version 15 of the HiPer Silicon design suite. HiPer Silicon v15 gives designers a complete analog design flow from schematic capture, circuit simulation, and waveform probing to physical layout and verification. HiPer Silicon v15 full-flow design suite is available now for the Windows operating system. A Linux version will be available later.

Tanner EDA HiPer Silicon Design Suite - W-Edit

HiPer Silicon v15 Features

  • TCL-based T-Cells
  • Import Calibre rule sets into Interactive DRC
  • Schematic-driven placement – relative position and rotation taken from schematic symbol
  • HiPer DevGen – differential pairs, current mirrors, MOSFETs and resistors
  • SDL Router improvements – single-layer (“river”) routing and double-via support
  • Integrated Verilog-A and SPICE views
  • User-defined netlisting priority of different views
  • Spice Wizard added to “Additional SPICE Commands” dialog
  • Model Explorer (S-Edit and T-Spice): view model and device parameters
  • WITH NEIGHBOR is now supported
  • REGION CENTERLINE option for INT, EXT, ENC rules is now supported
  • Labels devices by placing port opjects
  • Device and node counts are now written in the netlist
  • W-Edit simulation results viewer and Waveform Analysis Platform
  • Built-in measurements
  • Scripting
  • T-Cell based device generation

More info: Tanner EDA