Synopsys introduced the DesignWare DDR multiPHY. The IP solutions are mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L (1.35V DDR3), DDR3U (1.2xV DDR3), DDR2, Mobile DDR and LPDDR2 SDRAM Memories up to 1066Mbps data rates. Synopsys DesignWare DDR multiPHY IP solutions are designed to support a broad range of DDR SDRAM standards in a single PHY without sacrificing power consumption or silicon area. The DesignWare DDR multiPHY is available now.
DesignWare DDR multiPHY Overview
- When combined with a DesignWare Universal DDR digital controller core and Verification IP Synopsys provides a complete multi-protocol DDR interface IP solution
- Scalable architecture that supports from 0 to 1066 Mbps
- DFI 2.1 interface to controller
- Flexible, hardened macro approach: Three macro libraries are used to build the PHY, the application specific I/Os, Delay Locked Loops (DLLs) and Interface Timing Module (ITM) libraries
- Uses only 4 layers of metal for ITM and DLL
- Uses only 6 layers of metal for I/O cells
- Low latency
- Precision analog DLLs results in ultra low jitter
- Real time DQS drift detection and compensation
- Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
- Permits operating with SDRAMs using data widths narrower than the compiled data width (for example, a 32-bit interface can use just 16 bits to interface to a 16-bit wide SDRAM)
- At-speed loopback test mode for production test
- Low area and low power architecture
- Application specific multi-protocol DDR I/O library featuring PVT independent ZQ/RZQ programmable ODT and drive strength
- Area optimized I/O
- I/O retention mode
- Optional DDR signal integrity service is available to assist customers with the integration of the PHY into their SoC, package and printed circuit board environments
The DesignWare DDR multiPHY enables designers to target different DDR types for a single chip through simple software control. This capability makes it extremely flexible to integrate into an extensive array of applications such as consumer electronics, mobile, networking, server, computing, commercial/industrial and automotive applications. The DesignWare DDR multiPHY supports data rates from 0 to 1066 Mbps and offers a DFI 2.1 compliant interface to the memory controller.
The DesignWare DDR multiPHY is architected for extremely low power consumption and features Delay Lock Loop (DLL) bypass modes for operation below 200 MHz. It also features an I/O retention mode that allows the chip’s power supplies to be shut down completely while a small number of I/Os remain powered on to keep the external SDRAMs in self refresh mode. The DesignWare DDR multiPHY is designed to support the anticipated DDR3U standard operating at 1.2 or 1.25 V. In addition, the DesignWare DDR multiPHY provides built-in data training circuits to enable in-system calibration, providing optimized system-level timing without material interaction with the memory controller.
More info: Synopsys