The Embedded Microprocessor Benchmark Consortium (EEMBC) is developing new benchmarks that will track the performance of embedded processors with floating-point hardware units. Floating point (FP) refers to the ability of an embedded processor to crunch numbers that are too large or small to be represented as integers. Many embedded processors include hardware FP units (FPUs) to enable higher levels of precision. The new EEMBC benchmarks will enable embedded system developers to evaluate FPU performance on the basis of consistent and controlled data.
The floating point suite will likely address applications like DSP filtering, audio encoding, video encoding, and PID motor control. The suite is also planned to include a series of generic kernels such as bi-cubic filtering and FFT, which are particularly revealing of FPU performance. The benchmarks will also measure the performance delta between single (32-bit) and double (64-bit) precision.
EEMBC’s FP working group is actively looking for participants to further define and elaborate the new FP benchmark suite. Participation is open to all EEMBC subcommittee and Board of Directors members. EEMBC also is seeking contributions of benchmark kernels from the embedded industry at large. Leaders of the EEMBC workgroup developing the new benchmarks are Brian Jeff of ARM and Ron Olson of IBM, whose companies are founding members of the EEMBC Board of Directors.
EEMBC, the Embedded Microprocessor Benchmark Consortium, develops benchmark software to help designers select the right embedded processors for their systems. Benchmark algorithms and applications developed by EEMBC are organized into benchmark suites targeting telecommunications, networking, digital media, Java, automotive/industrial, consumer, and office equipment products.