Synopsys Design Compiler 2010

Synopsys introduced Design Compiler 2010. The tool enables RTL designers to perform floorplan exploration within the synthesis environment to efficiently achieve an optimal floorplan. Design Compiler’s new scalable infrastructure tuned for multicore processors results in 2X faster synthesis runtimes on four cores. Design Compiler 2010 reduces iterations and run times in physical implementation.

Synopsys Design Compiler 2010 Features

  • Two fold speedup in the synthesis and physical implementation flow
  • Extends topographical technology to further optimize its links with IC Compiler
  • Tightens correlation down to 5%
  • Streamlines the flow and speeds up placement in IC Compiler by 1.5X
  • Provides RTL designers access to IC Compiler’s floorplanning capabilities from within the synthesis environment
  • With the push of a button, designers can perform what-if floorplan exploration
  • Identifies and fixes floorplan issues early and achieves faster design convergence
  • Includes a new, scalable infrastructure designed to deliver significant runtime speedup on multicore compute servers
  • Employs an optimized scheme of distributed and multithreaded parallelization techniques
  • Delivers an average of 2X faster runtime on quad-core compute servers while achieving zero deviation of the synthesis results

More info: Synopsys