Tensilica launched the third generation of their Diamond Standard controllers. The Diamond Standard processor cores is based on a common Xtensa architecture and provides the price/performance/low-power required for a wide range of embedded control functions in today’s compute-intensive dataplane functions. Improvements in this third generation of Diamond Standard controllers deliver up to 15% faster clock speed, up to 20% smaller die area and up to 15% less power consumption. The Diamond Standard processors are available now.
Diamond Standard Cores
- Diamond 106Micro
An ultra-low-power small cache-less controller with memory protection, an iterative 32×32 multiplier, 15 interrupts, an integrated timer, and on-chip debug hardware that achieves Dhrystone 2.1 results of 1.22 DMIPS/MHz
- Diamond 108mini
Features a 32-bit integer divider, dual local data RAMs, 22 interrupts, three integrated timers, and dual 32-bit GPIO (general-purpose input/output) ports and achieves Dhrystone 2.1 results of 1.34 DMIPS/MHz
- Diamond 212GP
Features data and instruction caches and 16-bit DSP instructions and achieves Dhrystone 2.1 results of 1.38 DMIPS/MHz
- Diamond 233L
Same features as a Diamond 212GP and adds a Memory Management Unit (MMU) optimized for Linux operating systems
- Diamond 570T
A a three-issue VLIW (very long instruction word) core with dual 32×32 MULs and 16 Kbyte, 2-way set associative instruction and data caches, which achieves Dhrystone 2.1 results of 1.59 DMIPS/MHz
The Diamond Standard processors were designed with easy SOC (system on chip) integration in mind. All of the Diamond controllers are available with support for AMBA AHB-Lite and AXI bridges with asynchronous or synchronous clocks. In addition, on the Diamond 108Mini, 212GP, and 570T, designers can bypass the system bus altogether in order to achieve much higher input/output I/O bandwidth and seamless integration with RTL via direct GPIO connection interfaces for data and system monitoring and control. The Diamond 570T also provides 32-bit FIFO interfaces for direct data I/O (input/output) interface with other system blocks without using the system bus.
More info: Tensilica