Synopsys and imec will collaborate to accelerate the development of 3D stacked IC technologies. Synopsys TCAD (Technology Computer-Aided Design) finite-element method tools will be used for characterizing and optimizing the reliability and electrical performance of through-silicon vias (TSVs). The collaboration will accelerate the development of 3D stacked IC technologies.
3D stacked IC complements conventional transistor scaling and allows multiple chips to be stacked and integrated into a single package. The technology reduces form factor and power consumption, and increases bandwidth of inter-chip communication by minimizing connections through the circuit board with high parasitic capacitance.
3D stacked IC introduces a number of new issues that can potentially affect its reliability and performance. The collaborative research to address these issues will take place at imec, where silicon wafers with test structures will be manufactured and tested, and Synopsys’ TCAD tools will be used to model the TSVs in the chip stacks to optimize 3D stacked IC performance and reliability.
The collaboration between Synopsys and imec will speed up the development of through-silicon via technologies and will in turn facilitate the adoption of 3D stacked ICs in the semiconductor industry.