Forte Design Systems released the latest version of CellMath Designer datapath synthesis and Cellmath IP software. The CellMath family enables register transfer level (RTL) designers to reduce area, improve performance and lower power consumption for their existing datapath-intensive design blocks. U.S. pricing starts at $120,000 for a one-year, time-based license.
The latest version of CellMath Designer provides more automation to get users to optimal results with less effort. Other features include improved RTL code optimizations, a new bi-directional retiming algorithm and more scripting control, which mean that existing RTL designs can be used with no modifications. For existing users, CellMath Designer’s multiplexor synthesis capability has been extended. This will provide more optimal results when optimizing across many levels of multiplexors, including recognizing complex pipeline enable signals formed from multiple levels of logic to improve ease of use and overall quality of results (QoR).
With CellMath Designer, engineers have complete control over which parts of the design are described in RTL code and which at the gate-level, along with control over which carry-save outputs include final additions. This enables designers to break verification problems into a chain of simpler/smaller steps that formal verification software can manage. With these new features, unresolved verification tasks can be turned from inconclusive to equivalent.
CellMath Designer utilizes optimal, mathematically designed arithmetic operators and functions to improve overall quality of results in datapath-dominated designs. Together with CellMath Designer’s datapath synthesis capabilities, designers find that utilizing CellMath IP operators improves overall QoR, especially power, on existing RTL designs.
CellMath IP includes patented arithmetic architectures for floating-point, fixed-point and integer-based designs, and is being used in millions of leading-edge devices around the world.
More info: Forte Design Systems