ESD Design for High Speed Interfaces: Signal Integrity Considerations

NXP Semiconductors has an archived webinar about maintaining signal integrity when placing ESD devices on high speed differential signals. Topics covered in the webcast include: Capacitance, inductance, and methods of impedance matching, maintaining eye openings, and minimizing jitter and skew. During the online seminar, NXP will compare signal integrity challenges with different ESD solutions.

Signal Integrity Considerations Webinar Overview
Next generation interfaces such as HDMI 1.4, USB 3.0, eSATA, and DisplayPort present serious challenges to system designers trying to provide adequate protection against ESD threats. In the earlier Part 1 of this series, we focused on techniques for ensuring adequate levels of protection for these high speed interfaces. In Part 2, we turn our attention to maintaining signal integrity when placing ESD devices on high speed differential signals.

ESD Design for High Speed Interfaces Webcast Topics

  • Capacitance, inductance, and methods for impedance matching
  • Maintaining eye openings, minimizing jitter and skew
  • Looking beyond the specifications – comparing signal integrity challenges with different ESD solutions

More info: ESD Design for High Speed Interfaces: Signal Integrity Considerations – NXP Webinar