Aldec is offering a webinar, Automatic Generation of Flexible Testbenches. The webcast will take place February 18, 2010. There will be two sessions. Session 1 will take from 3:00 pm to 4:00 pm (Central Europe Time Zone) and Session 2 will take place 11:00 am to 12:00 pm (Pacific Standard Time Zone). The online seminar will be presented by Mr. Jerry Long, Applications Engineer at EMA Design Automation.
Design teams face increased challenges while working on projects that are constantly increasing in size. One of the most important challenges is efficient verification; automatic generation of highly-functional testbenches that can be easily modified and reused is a very important task to assure productivity. The webinar will present new a solution called Verification Modeler from EMA Design Automation that allows automatic creation of advanced testbenches based on a graphical timing diagram.
Verification Modeler extracts protocol data to build Bus Functional Models and Monitors, creates a transaction layer of the testbench using features of SystemC or SystemVerilog and allows both random and directed testbench data generation. The testbenches generated by the Verification Modeler work with any Verilog and VHDL RTL designs and can be used at any level of design. The webinar will conclude with a quick demonstration of EMA’s Verification Modeler working with together with Aldec Active-HDL.
Automatic Generation of Flexible Testbenches Webinar Agenda
- The Testbench Functional Verification GAP
- Flexible Testbench Structure
- Advantages of Transaction-based Approach
- Working with Verification Modeler
- Question and Answer Session
More info: Aldec