Sapphicon Semiconductor and AWR teamed on process design kits (PDKs) for AWR software that support Sapphicon’s advanced SoS processes. AWR’s Analog Office RFIC design software is used to develop Sapphicon PDKs because of its ability to provide extremely accurate models. AWR/Sapphicon PDKs are available immediately to select, pre-qualified joint customers.
Sapphicon presently offers AWR PDKs for all variants of its 0.25-µm process and is currently working on PDKs covering its 0.5-µm high- frequency RF/mixed signal complementary metal oxide semiconductor (CMOS) processes.
SoS is an ideal process for high-frequency and mixed-signal devices as its insulating substrate eliminates parasitic capacitance from the circuit, which enables higher frequencies, low power consumption, and high Q passives (e.g., inductor QL greater than 40 at 2 GHz) to be achieved. Transistors created using SoS technology also have much lower junction capacitance and thus have fewer non-linearities at high frequencies than those manufactured with standard CMOS processes.