Cadence Encounter Digital Implementation System 9.1

Cadence Encounter Digital Implementation (EDI) System 9.1 is a digital design, implementation, and verification environment for the development of large-scale, complex SoCs. EDI System 9.1 helps designers develop low power and mixed signal SoCs at 32- and 28-nanometer with hundreds of millions of gates, including hundreds of IP elements and embedded processors.

EDI System 9.1 combines automatic floorplan synthesis, data abstraction modeling, and new concurrent macro- and standard cell placement. With EDI System 9.1, designers can quickly find and implement the optimal physical architecture of a chip.

EDI System improves designer productivity by broadening its integrated suite of native signoff capabilities. Building on its existing foundry certified power, timing, and signal integrity (SI) signoff capabilities, EDI System 9.1 now adds silicon-accurate extraction and design-for-manufacturing (DFM) analyses to complete the picture. DI System 9.1 enables designers to design, implement, and verify chips 2-3X larger and 2X faster than traditional flows and with superior quality of silicon. The tight integration of signoff checks in the implementation phase enables exceptional correlation to final silicon, thereby reducing the potential for expensive silicon respins.

The new integrated, turbo QRC extraction capability provides fast in-design, incremental signoff extraction and drives fast and convergent design closure for physical and electrical design requirements. Also, since foundries now mandate DFM checks in the physical design flow at 40-nanometer and below, built-in, foundry-certified DFM analysis is a must-have at these nodes. The new integrated DFM capability – turbo Litho Physical Analyzer – brings built-in litho pattern intelligence and filtering to the interconnect routing phase, enabling automatic detection, prevention, and correction of potential litho hotspots before they happen. This capability improves DFM and yield for advanced 40-, 32- and 28-nanometer nodes and is significantly faster than traditional lithography signoff tools.

EDI System 9.1 also extends its innovative memory architecture to achieve significant gains in memory capacity, acceleration in single-CPU operations, and improved performance scalability across its multi-CPU backplane, bringing efficient parallel processing throughout the design flow.

More information: Cadence