Nanometer IC Variation Analysis Design Flow

Berkeley Design Automatio and Solido Design Automation teamm on a validated flow for rapid reduction in variation risk in nanometer designs at the transistor level. In the solution, Variation Designer utilizes the AFS Platform. The result is variation analysis capabilities that enable designers to rapidly reduce variation risk.

Variation Designer, along with Solido’s PVT (process, voltage, temperature) Corner, Statistical, and Proximity applications packages can be deployed for transistor level design to account for global, local, environmental and proximity related variation effects. The benefit of the solutions is improved designs and reduced variation risk in less time. Variation Designer is used across the transistor level design cycle – from PVT corner simulations to statistical analysis – to determine mismatch effects or yield.

The Analog FastSPICE Platform (AFS Platform) is the industry’s only unified circuit verification platform for analog, mixed-signal, and RF design. It always delivers true SPICE accurate results, while providing 5x-20x higher performance than traditional SPICE, >10 million-element capacity, and the industry’s only comprehensive device noise analysis. The AFS Platform is a single executable that uses advanced algorithms and numerical analysis to rapidly solve the full-circuit matrix and original device equations without any shortcuts. The AFS Platform includes licenses for AFS Nano SPICE simulation, AFS circuit simulation, AFS Co-Simulation, AFS Transient Noise Analysis, and AFS RF Analysis.

More information: Berkeley Design Automation | Solido Design Automation