AWR Design Environment Version 9.01

AWR launched version 9.01 of the AWR Design Environment (AWRDE). The latest release of AWRDE features over 100 enhancements that increase productivity. The new features include enhancements to AWR’s APLAC harmonic balance engine and AXIEM 3D planar electromagnetic (EM) simulator.

AWRDE Version 9.01 includes a new harmonic balance mode to the APLAC simulator that increases simulation speed for microwave nonlinear circuits, especially when there are an equal number of linear and nonlinear models or more linear than nonlinear models. In addition, AXIEM now supports series ports, which enables designers to use the software to design two-port chip components.

New or enhanced elements include the addition of an XdB compression point control block that lets designers plot all nonlinear measurements from a given schematic at “X” dB into gain compression, and an arbitrary, user-specified bit sequence (V_ARBS) and pseudo-random bit sequence (V-PRBS) that are additional voltage sources available to the user.

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