Synopsys DesignWare 3G DigRF, CSI-2 Controller, and D-PHY MIPI IP
Synopsys introduced three new DesignWare MIPI IP. The DesignWare consists of 3G DigRF Controllers and PHYs for MIPI DigRF V3 standard interface; CSI-2 Synthesizable controller for MIPI CSI-2 Host application; and D-PHY Physical Layer for MIPI CSI-2, DSI, and UniPro standard interfaces. The DesignWare 3G DigRF master and slave controllers and PHY, CSI-2 host controller and D-PHY are available now in 65nm and 40nm process technologies.
DesignWare 3G DigRF IP Features
- Silicon-proven Master and Slave Controller IP compliant with 3G DigRF v3.09 Specification
- Master controller handles frame construction and serialization in the transmit channel and header decoding and payload processing in the receive channel
- Basic handset and local diversity with multiplexed interface
- AMBA-APBTM slave interface for configuration, control and transmission of link commands
- Silicon-proven dual mode PHY
- 312Mbps data rate
- Support sleep and shutdown modes
- Minimized interface pin-count
DesignWare CSI-2 IP Features
- Compliant with MIPI csi-2 Interface Specification, rev. 1.0
- PPI interface to D-PHY
- Configurable from 1 to 4 data lanes
- Programmable multi-lane merging
- Supports all primary and secondary CSI-2 Data Formats
- Short and Long packet formats
- Detection of Low Power and Ultra Low Power modes
- Error detection and correction with interrupt at PHY, Packet, Line and Frame level
- 32bit Pixel Output format
- AMBA-AHB control and configuration
- Packaged with Synopsys CoreConsultant
DesignWare D-PHY IP Features
- Compliant with MIPI D-Phy Interface Specification, rev. 1.0
- Fully integrated hardmacro
- Up to 1Gbps per lane
- 250 Mbps in reverse direction
- Aggregate throughput up to 2Gbps in 2 Data lanes
- Protocol Peripheral Interface (PPI)
- Low power Escape modes and ultra Low Power Modes
- Shutdown mode
- SCAN and Loopback BIST modes
- Extensive access to internal programmability registers
The Mobile Industry Processor Interface (MIPI) Alliance defines a set of standard hardware interfaces between mobile baseband processors, RF integrated circuits (ICs) and peripherals typically found in smartphones and multimedia handheld devices.
More information: Synopsys
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