Real Intent Ascent Lint v1.2

Real Intent launched Ascent Lint Version 1.2 for early functional verification. Ascent Lint v1.2 performs syntax and semantic Lint checks for complex SoC designs. Ascent Lint now offers rules from STARC Policy, Verilog and SystemVerilog Gotchas, Reuse Methodology Manual (RMM), Principles of Verifiable RTL Designs, and rules based on Real Intent industry expertise.

Ascent Lint features an extremely fast engine, low noise report, and is easy to use for debugging. Ascent Lint 1.2 is available now.

Ascent Lint v1.2 Rules Highlights

  • Legal but dubious modeling indicating probable errors
  • Differences between simulation and synthesis semantics
  • Naming and RTL coding conventions
  • Subset restrictions to enforce modeling clarity and reduce complexity
  • Opportunities to improve simulation performance
  • Operations with hidden or expensive implementation costs
  • Downstream tool flow issues
  • Network and connectivity checks for clocks, resets, and tristate-driven signals
  • Module partitioning rules
  • Testability

More info: Real Intent