Magma Issues Call for Papers for 2010 MUSIC User Conferences

Magma Design Automation issued a call for papers for the 2010 Magma Users Summit on Integrated Circuits (MUSIC) user conferences. MUSIC Silicon Valley will be held at the Doubletree Hotel in San Jose on March 10, MUSIC China will be on March 23 at the Shanghai Hotel in Shanghai, and MUSIC India will take on March 30 at the Taj Residency in Bangalore. In a new offering for the 2010 MUSIC events, Magma is requesting additional topics from users. Users whose suggested topics are added to the agenda will win a Dell Inspiron Mini netbook.

Suggested Technical Papers and Presentations Topics

  • Full-chip hierarchical planning, prototyping and implementation
    • Hydra-based automated partitioning, floorplanning
    • Black box and GlassBox methodologies
    • GUI-driven interactive floorplanning and prototyping
    • Rectilinear block editing and pin optimization
    • Pad definition and I/O placement
    • Accommodating late-arriving changes vs. ECOs
  • Front-end design, including:
    • RTL, data path, low power, hierarchical or flat synthesis
    • Synthesis for high-performance designs
    • Synthesizing very large designs
    • Setting up a synthesis flow – tips, techniques and compromises
    • Migrating from legacy synthesis flows – what to keep, what to throw away and what to watch out for
    • Measuring and improving the quality of your ASIC
  • Timing constraints
    • Timing constraint generation and verification
    • Debugging timing problems in front-end design
  • Physical implementation, including:
    • Clock tree synthesis
    • Nanometer design including OCV analysis and timing optimization, and concurrent multi-mode and multi-corner (MM/MC) analysis and optimization
  • Low-power design using:
    • Low-power design techniques for consumer devices (wireless, handheld, etc)
    • Multi-voltage domain design implementation and validation
    • Automatic power-grid synthesis and power budgeting
    • Power gating, automatic clock gating
    • Low power system architectures
    • Leakage power minimization with multi-Vt libraries and MTCMOS switch insertion and analysis
    • Automatic decoupling capacitor placement, analysis and optimization
    • Low power via dynamic voltage frequency scaling (DVFS)
  • Analysis and sign-off, including:
    • Correlation flow setup challenges and solutions
    • Managing timing analysis and sign-off with multiple (many) MM/MC scenarios
    • Leveraging Sign-off in the Loop technology
    • Signal integrity and power integrity
    • Hierarchical timing analysis
    • Modeling OCV, crosstalk, IR-drop effects in the timer
    • Thermal effects on timing and leakage
    • AC/DC electromigration analysis
  • Physical verification:
    • 65/45/28-nm physical verification challenges
    • Physical verification sign-off during implementation
    • Transistor and interconnect extraction at 45 nm and at 28 nm
    • Design rule manual – elements of common model-based rule language
  • Designing for better yield
    • Measuring and improving the yield of your ASIC
    • Yield analysis and optimization leveraging functional cell yield optimization, CAA-driven wire spreading and OPC-aware routing
  • Analog design automation
    • Mixed-signal design
    • Custom layout editing
  • Next-generation circuit simulation
    • Analog simulation

More info: MUSIC (Magma Users Summit on Integrated Circuits)