Perfectus Technology PCI Express Gen3 Verification IP
SystemVerilog-based and Open Verification Methodology (OVM)-compliant PCI Express Gen3 verification IP (Genie-PCIe3 VIP) is now available from Perfectus Technology. Genie-PCIe3 VIP helps designers accelerate the verification of PCI Express Gen3-based products. Genie-PCIe3 features a complete set of intelligent verification components for verifying PCI Express 1.1/2.0/3.0 and SR-IOV-based designs and it works in any verification environment, including SystemVerilog and OVM methodology. PCIe Gen3 VIP is available immediately.
Genie-PCIe3 is fully compliant to the PCI Express Gen3. The Test Suite and Interface Inspector enable developers to comprehensively test PCI Express Gen3 Root Complex, Endpoint, Switch, SR-IOV Endpoint, and PHY designs against the vast requirements set forth by the PCIe Gen3 specification. The Root complex and End Point Models, Comprehensive Test Suite for unit level and System Level testing and Interface Inspector help ensure robust verification, maximum functional coverage, complete protocol compliance, and error testing.
Genie-PCIe3 VIP has a rich set of constrainable parameters, sequence library, powerful error injection capabilities, APIs and Callbacks for user configurability. The VIP is configurable and extensible to satisfy each specific verification environment’s requirements. Another important feature of Genie-PCIe3 is the statistical reports generated by the Genie-Interface-Inspector.
Genie-PCIe3 Reports
- Functional Coverage report which helps to identify what functionality has been tested
- Error Inspection report which specifies the errors that were tested and errors that were not tested
- Protocol Inspection report which shows the percentage of PCIe 3.0 specification compliance
- Features Coverage report which shows the percentage of features covered
More info: Perfectus Technology
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