Aldec introduced ALINT 2009.10 Design Rule Checking application. The product includes “best-practice” design rules for fast design closure of safety critical DO-254/ED-80 Avionics designs. ALINT is Design Rule Checking software for fast design closure. ALINT analyzes and detects issues early in the design and verification cycle, and checks HDL source code of complex ASIC, FPGA, and SOC designs. It detects such problems as poor coding styles, improper clock and reset management, simulation and synthesis problems, poor testability, and source code issues throughout the design flow.
- Fast Design Analysis of complex ASIC/FPGA/SOC designs
- Comprehensive Set of Design Rules
- Integrated Results Analysis and Debugging Environment
- IEEE VHDL, Verilog and Mixed-Language support
- User-defined Design Rules
- DO-254 Rule Set
- Linux and Windows Vista/XP/2003/2000 32/64 bit support
- STARC VHDL or Verilog rule plug-ins
- DO-254/ED-80 VHDL or Verilog rule plug-ins
ALINT 2009.10 offers a set of VHDL or Verilog design rules optimized to detect HDL code, design and verification issues including: design recoding practices, design reviews and safe synthesis guidelines. The new DO-254 design rule plug-in provides guidance to help achieve DO-254/ED-80 compliance for FPGA designs that reside within a system.
ALINT 2009.10 with VHDL or Verilog DO-254 design rule plug-in is available now.
More info: Aldec