Maia Functional Verification Tool

Maia EDA introduced the Maia functional verification tool. Maia uses a description of the expected behavior of a device to automatically create a complete self-checking reactive testbench, so freeing engineers from the time-consuming, complex, and error-prone task of manual testbench creation. The tool has been designed to enable both engineers and non-engineers to quickly verify modules and sub-systems, and is initially being offered without cost by the company, allowing trial without registration or risk.

Maia is primarily targeted at hardware engineers who write and need to verify their own RTL code, but a key benefit of the tool is that it can be used by staff who have no knowledge of Verilog or VHDL, and who have only minimal programming skills. Modules and subsystems can be verified by anyone who has access to a specification, and who can construct sequences of vectors corresponding to the device inputs, and expected outputs.

Maia automates the creation of testbenches by using declarative and fifth-generation language (5GL) techniques. An expected ‘solution’ is specified by listing sequences of inputs and expected outputs as vectors. Maia treats the vectors as constraints, and creates the corresponding self-checking testbench, automating the processes of driving and testing timed device inputs and outputs, clock and reset generation, stability checking, pipeline handling, internal signal probing and forcing, time handling, and error reporting.

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