Pin-level SystemC Models of Xtensa Customizable Dataplane Processors
Tensilica introduced pin-level SystemC models of the Xtensa customizable dataplane processors (DPUs). The pin-level models are a natural extension of Tensilica’s pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC). They enable designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing RTL simulators. The models also do not require the usage of any specialized hardware/software co-simulation tool.
IC designers can now use Tensilica’s fast, instruction-accurate functional models for early design exploration and software development, more detailed pipeline accurate models with TLM interfaces connected to other devices modeled in SystemC, or cycle-accurate pin-level SystemC models to verify the interconnection of the processor with tightly coupled hardware blocks via Verilog simulation. The models can be run inside all of the leading RTL simulator tools including Incisive Enterprise Simulator from Cadence, Questa from Mentor Graphics, and the VCS functional verification solution from Synopsys.
Pin-level SystemC modeling provides a solution to engineers who want to exercise the connections between the processor and the external logic with real software running on the target. Tensilica’s pin-level XTSC simulations are available now as an option to Tensilica’s software developers’ kit.
More info: Tensilica
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