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Intel Westmere 32nm Layout and Design for Manufacturability Analysis

Posted by Ken Cheung in Research on Thursday, December 3, 2009

Chipworks announced their Design for Manufacturability (DFM) analysis of Intel’s 32 nm Clarkdale/Westmere microprocessor from the Core i5 660. The analysis combines a standard reverse engineering report with the ICWorks Surveyor format. ICWorks Surveyor is a software tool that allows the engineer to navigate thousands of images stitched together into a massive floor-plan across all the metal layers of the device. Intel Westmere 32 nm Layout and Design for Manufacturability Analysis is now shipping.

Intel 32 nm Core i5 660 Microprocessor orthogonal metal lines

Chipworks imaged portions of the Intel chip at the lower metal, gate, and substrate levels. In addition, bevels were taken from several regions to follow the DFM features across all layers. Chipworks analysis has been expanded to include this specialized DFM capability for companies in the semiconductor industry who use our analysis to reduce the risk of their billion dollar long-term investments, save millions in product and process development costs, and earn millions in new revenue by getting to market faster with better products.

Included in the report:

  • A layer-by-layer look at the detailed design rules using SEM and TEM microscopes
  • Layout of standard logic and SRAM cells
  • Analysis of key dummy features

DFM considerations are critical for all stages in the production of a microchip and the processes being employed at the latest advanced geometries. The key features of the DFM report include:

  • Analysis of the standard design rules
  • Analysis of the DFM features
  • Analysis of standard logic and SRAM cells
  • ICWorks Surveyor Image Mosaic of over 7 GB of SEM images

More info: Chipworks

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