At the IEEE International Electron Devices Meeting (IEDM), engineers from SEMATECH’s Front End Processes (FEP) program will present technical papers revealing research breakthroughs. SEMATECH experts will report on low defect density high-k gate stacks for alternative III-V channel materials and non-planar devices, and discuss a new dry etch approach to minimize etch related leakage — a significant process technology advancement for next-generation logic and memory technologies. The IEDM Conference will take place December 7-9, 2009, at the Hilton in Baltimore, MD.
SEMATECH will also host an invitational pre-conference workshop entitled “Emerging Technologies in Solid State Devices” from December 5-6. The two-day workshop will focus on technical and manufacturing challenges affecting emerging memory technologies, energy-efficient devices, and III-V channel materials in CMOS devices. Co-sponsored by Tokyo Electron Limited and Aixtron AG, the workshop will feature experts from industry and academia debating the challenges and opportunities in these areas in a series of presentations and panel discussions.
SEMATECH FEP Sessions at IEDM Conference
- Impact of Dipole-Induced Dielectric Relaxation on High-frequency Performance in La-Incorporated HfSiON/Metal Gate nMOSFET
Session 6, Monday, Dec. 7 at 2:25 p.m.
Investigates the relationship of high frequency and dielectric relaxation of dipoles in La-doped HfSiON devices. This work was done in collaboration with POSTECH team from Korea.
- Dual Channel FinFETs as a Single High-k/Metal Gate Solution Beyond 22nm Node
Session 12, Tuesday, Dec. 8 at 11:10 a.m.
Shows that pFinFETs with a SiGe channel on insulator (SiGeOI) fabricated using standard CMOS processing exhibit 3.6X better hole mobility than silicon (100) while controlling the threshold voltage in single high-k and metal gate stacks.
- InGaAs MOSFET Performance and Reliability Improvement by Simultaneous Reduction of Oxide and Interface Charge in ALD (La)AlOx/ZrO2 Gate Stack
Session 13, Tuesday, Dec. 8 at 10:45 a.m.
Reports on the performance and reliability of ZrO2/In0.53Ga0.47As MOSFETs. An amorphous (La)AlOx interlayer at the ZrO2/In0.53Ga0.47As interface is key to reducing border and interface traps and moving the ZrO2 fixed charge away from the In0.53Ga0.47As.
- A Novel Damage-Free High-k Etch Technique Using Neutral Beam-Assisted Atomic Layer Etching (NBALE) for Sub-32nm Technology Node Low Power Metal Gate/High-k Dielectric CMOSFETs
Session 17, Tuesday, Dec. 8 at 3:35 p.m.
Demonstrates a novel damage-free neutral beam-based atomic etching process that successfully removes the residual high-k dielectric layer after gate patterning. This research was a collaborative effort with Sungkyunkwan Univeristy, Korea, and was partially supported by the National Program for Tera-Level Nano devices of the Korea Ministry of Science and Technology.
The IEDM Conference is ideal for industry professionals in the areas of exploration of design, manufacturing, physics, and modeling of semiconductors and other electronic devices. The conference spotlights leading work from the world’s top electronics scientists and engineers; it is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities, and other research institutions, many of whom are research partners.
More info: SEMATECH