Improving IP Quality Versus Losing Design Productivity
Satin IP Technologies will be in a panel at the IP-Embedded Systems Conference in Grenoble, France on December 1, 2009 from 17:15 to 18:45. They will discuss improving intellectual property (IP) quality without losing design productivity. The panel (entitled Improving IP Quality vs. Losing Design Productivity – What Are the Tradeoffs?) will discuss issues that arise when time-to-market and cost reductions dominate IP design and integration, since instituting design practices for enhanced quality can be seen as overhead by engineers and engineering managers.
This panel will use real world examples from IP buyers and sellers to address questions like: How do you balance the cost of addressing IP quality up front vs. after tape-out? Where do semiconductor companies and IP vendors usually set the cursor? What are the most important quality issues to address? How helpful are the quality standards in addressing key issues? Is there any way to reduce the impact of quality management on design schedules and costs?
Improving IP Quality Panelists
- Chairperson: Phil Dworsky, Director of Strategic Alliances at Synopsys
- Philippe Di Crescenzo, Director of Engineering, Arteris
- Kathryn Kranen, President and CEO, Jasper Design Automation
- Joachim Kunkel, Vice President and General Manager, Solutions Group, Synopsys
- François Rémond, CAD and Design Methodology Director, STMicroelectronics
- Michel Tabusse, President and CEO, Satin IP Technologies
Panel: Improving IP Quality vs. Losing Design Productivity – What Are the Tradeoffs?
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