A new capability in DFTMAX compression reduces the cost of test for designs and methodologies that mandate very few test pins. Extending Synopsys’ patented adaptive scan technology with a high-performance, low-pin interface to the tester enables designers to achieve predictable compression of up to 100X or more with only one pair of test data pins. DFTMAX compression now delivers even greater test time and cost savings for today’s challenging designs.
The new, high-speed, low-pin tester interface generated by DFTMAX compression serializes the test data, enabling up to 100X or more test data volume and test application time reduction for these pin-limited test methodologies. Built into the Galaxy Implementation Platform to eliminate time-consuming iterations between synthesis, scan insertion and physical implementation, DFTMAX compression and TetraMAX ATPG provide designers with a comprehensive solution for meeting their most challenging quality and cost goals for test.
Current trends are accelerating the need for pin-limited test. Increased focus on packaging costs and tighter form factors for portable applications are leading to driving more stringent packaging constraints, resulting in few pins allocated for test. To manage complexity, designers are increasingly deploying core-based methodologies with multiple embedded compressor-decompressors (CODECs) that reduce the number of chip-level test pins available to each CODEC. Multi-site testing, a technique that targets multiple die simultaneously to reduce test time, is also stimulating the demand for pin-limited test because each die has access to fewer tester channels.
More info: Synopsys