Cadence Design Systems introduced a comprehensive low-power design flow for engineers targeting the 65-nanometer process at Semiconductor Manufacturing International Corporation (SMIC). Based on the Cadence Low-Power Solution, the flow enables faster design of leading-edge, low-power semiconductors using a single, comprehensive design platform. The SMIC-Cadence Reference Flow 4.0 addresses the need for power-efficient design innovation with an advanced, automated low-power design capability.
Validation of the flow was accomplished through implementation of low-power chips utilizing SMIC’s in-house – designed 65-nanometer libraries, including effective current source model (ECSM) standard cells, power management cells, PLLs, SRAMs and I/O libraries. Low-power technologies employed in the design include power gating and multi-supply/multi-voltage (MSMV) techniques to reduce leakage and dynamic power consumption.
The Cadence Low-Power Solution provides a complete, silicon-validated front-to-back flow for designers targeting SMIC’s 65-nanometer process technology, including functional and structural verification, while increasing productivity. The 65nm SMIC design flow features the Cadence Low-Power Solution, with Encounter Conformal Low Power, Incisive Enterprise Simulator, Encounter RTL Compiler, Encounter Digital Implementation System, Cadence QRC Extraction, Encounter Timing System, and Encounter Power System.