Open-Silicon, MIPS Technologies, Virage Logic Team on Test Chips

Open-Silicon, MIPS Technologies, and Virage Logic teamed to develop test chips showcasing the companies’ technologies for building high-performance processor-based systems. The companies achieved successful 65 nanometer (nm) silicon testing of a processor test chip at 1.1GHz, making it one of the fastest processors built in a 65nm ASIC. In addition, the companies are now working on a follow-on 40nm device targeting frequencies in excess of 2.5GHz and providing over 5000 DMIPS of performance. Both efforts utilize Open-Silicon’s CoreMAX technology as well as the superscalar MIPS32 74K processor core, a fully synthesizable processor core widely used in high-end digital consumer devices, set top boxes, and networking solutions.

The 65nm test chip was designed to show how the companies’ technologies can be used to achieve top performance in a standard ASIC implementation. The 74K processor core is complemented with 32KB L1 instruction and data caches, a 512KB L2 cache, and system and memory controller blocks, and was implemented using TSMC’s 65nm GP process with standard 10 track libraries and Virage Logic’s SiWare Memory compilers. The companies have working silicon running at 1.1 GHz. To achieve this goal, Open-Silicon applied its patented CoreMAX performance enhancement technology to the design. This technology permitted the designers to build several hundred new standard cells targeted specifically at speeding up the design’s critical paths. This, along with the advanced SiWare Memory compilers and a triple Vt process option, allowed final design worst-case timing closure across all corners at 1.1GHz with standard ASIC margins.

The 40nm test chip in development is planned to reach silicon in the first quarter of 2010. The performance target is very high; frequencies above 2.5GHz are expected when selected from typical silicon, providing over 5000 DMIPS at top speeds. This test chip will include a floating point version of the 74K processor core, along with L2 cache, and system and memory controller blocks.

More info: Open-Silicon | MIPS Technologies| Virage Logic