Cadence Design Systems Allegro and OrCAD PCB Design Release 16.3

Cadence Design Systems introduced version 16.3 of the Allegro and OrCAD printed circuit board (PCB) software. The lates release includes new features and functionality designed to boost productivity and performance for PCB engineers. The Allegro and OrCAD PCB Design Release 16.3 offer PCB engineers the ability to miniaturize the footprint of end product and reduce the number of physical prototype iterations, making the design cycle more predictable. The Allegro and OrCAD PCB Design Release 16.3 will be available for download in early December 2009.

Cadence Design Systems Allegro and OrCAD PCB Design Release 16.3

The 16.3 release addresses increased functional and interconnect density through improvements for rigid-flex routing, extended high-density interconnect (HDI) rules, 3D viewing of PCBs, and asymmetrical clearance for RF circuits. Extended micro via stacking rules enable users to create the most difficult HDI designs, and multi-line curved bus routing that hugs the flex outline accelerates the creation of rigid-flex designs. In addition, an integrated 3D PCB viewer gives designers visibility into components and HDI micro via breakouts, thus eliminating unnecessary iterations with mechanical design teams. The Allegro PCB RF Option also helps engineers speed the time to create accurate RF circuits through the use of asymmetrical clearances for one or more RF elements.

The 16.3 release also include several productivity and usability improvements to the OrCAD family of products. OrCAD Capture CIS, for instance, now offers autowire capability to quickly add connections, as well as new 3D footprint viewing. OrCAD PCB Editor provides 3D viewing and “flip-board” design/editing and jumper support for single-sided PCB designs. OrCAD Signal Explorer has a revamped user interface, with drag-and-drop and copy-and-paste functionality, context-sensitive RMB functions and native IBIS model support.

The latest Allegro PCB Signal and Power Integrity software offer a new user interface and add stack-up-aware capabilities to the pre-route analysis environment. Buffer modeling standards are embraced through native IBIS and SPICE support, including Cadence Virtuoso Spectre Circuit Simulator models. Another improvement that boosts design cycle management is the ability to quickly scan a PCB with dozens of multi-gigabit signals and quickly determine where detailed analysis should be applied as signals are ranked according to their signal-to-noise ratio.

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