Synopsys has created an optimized reference implementation methodology for the ARM Cortex-A8 processor that achieves greater than 2GHz (4000 DMIPS) at 540mW. The result was accomplished by combining optimized methodology, tools, and ARM Physical IP to enable new classes of mobile and tethered devices requiring the combination of high-performance and energy efficiency. The Synopsys Galaxy Implementation Platform methodology (scripts and documentation) for the 2GHz ARM Cortex-A8 optimized implementation is available from ARM and Synopsys.
Synopsys and ARM have collaborated in a series of implementation case studies across methodologies, libraries and process technologies targeted at increased performance of a fully automated synthesizable ARM Cortex-A8 processor. To achieve optimized results, the Synopsys team used the Synopsys Galaxy Implementation Platform, including some of the latest 2009.06 Design Compiler Graphical, IC Compiler, StarRC and PrimeTime SI capabilities, ARM Physical IP libraries and memories for a 40nm foundry process together with highly tuned floorplan and design constraints. The ARM Cortex-A8 processor optimized implementation achieved greater than 2GHz in the typical corner on a 40nm process while consuming .24mW/MHz dynamic power and 57mW static power using less than 2% LVt cells.
The implementation team at Synopsys took advantage of the latest capabilities in the Galaxy Platform, including: library subset usage scenarios, delay performance versus cell area tradeoffs, cell placement density versus floorplan dimension tuning, leakage optimization techniques, multi-corner multi-mode (MCMM) optimization for better timing correlation and signoff optimization between IC Compiler and Prime Time, as well as the usage of the latest clock tree synthesis capabilities together with intelligent user clock constraints. The Galaxy Platform is a key component of Synopsys’ Eclypse Low Power Solution and the Lynx Design System.