Vertically Optimized 32/28nm Solution for Mobile SoC Design

Synopsys will take part in a technical session and breakfast at ARM TechCon3. ARM, the Common Platform (IBM, Chartered Semiconductor Manufacturing ,and Samsung Electronics) alliance, and Synopsys will discuss the new level of collaboration necessary to address the cost and technical challenges associated with advanced mobile SoC design and manufacturing. The event will take place Wednesday, October 21st, 8:30am – 10:30am at the Santa Clara Convention Center (Ballroom H).

Vertically Optimized 32/28nm Solution for Mobile SoC Design

  • HKMG Process Technology Enablement
    32/28-nanometer (nm) low-power/low-leakage, high-k metal-gate (HKMG) material science breakthroughs and synchronized foundry services through the Common Platform alliance
    Dr. Jaga Jagannathan, Director, 32/28 Technology Productization, IBM Semiconductor R&D Center

  • Foundation, Enhanced and Processor IP Enablement
    ARM high-performance, low-power processor architecture for mobile applications, and optimized suite of physical intellectual property (Physical IP) on Common Platform 32/28LP foundry process
    Dr. Dipesh Patel, Vice President of Engineering at ARM’s Physical IP Division

  • Tool, Connectivity IP and Flow Enablement
    Synopsys Lynx Design System, early tool, IP and flow enablement, and integration roadmap of Lynx, ARM processor and ARM Physical IP for the Common Platform’s 32nm/28nm high-k metal-gate (HKMG) process technology. Includes worked example of an ARM Cortex processor using the latest versions of the Synopsys Lynx Design System and ARM Physical IP in development for the Common Platform 32/28LP offering.
    Glenn Dukes, VP of Professional Services, Synopsys, Inc.

As semiconductor technology approaches fundamental physical limits and design complexity reaches unprecedented levels, a deeper type of technical alignment is essential. Attendees will learn how the extended collaboration among the seminar hosts enables designers to deliver optimized ARM processor-based 32/28LP mobile SoC designs while achieving faster time-to-market at reduced risk and design cost. The presenters will also explain how the collaboration is enabling a proven turnkey design solution for optimizing innovation and accelerating designs with best-in-class technology, physical and processor IP, and tool/flow solutions for the Common Platform’s 32nm/28LP high-k metal-gate (HKMG) process technology.

Other Synopsys ARM Techcon3 Conference Sessions

  • Optimized Implementation of GHz ARM Cortex-A9 Processor – High performance, with Low Power
  • Solving Common Power Management Verification Issues with ARM-based SoCs
  • Increasing Software Development Productivity with ARM and Synopsys Modeling Solutions
  • Optimized Implementation of GHz ARM Cortex-A8 Processor – High performance, with Low Power
  • High-Performance, Lower-Power, Reduced Route Architecture for the AMBA 3 AXI On-Chip Interconnect

More info: Synopsys