Tensilica announced the Xtensa 8 customizable processor. The Xtensa 8 low-power dataplane processor core (DPU) starts at a size of only 15,000 gates, consuming less than 0.05mm squared in 40nm process technology. It is one of the smallest licensable controller cores on the market. With power dissipation starting at only 12 µW/MHz, it is also one of the lowest power licensable 32-bit architectures. The Xtensa 8 customizable processor will be available later this month.
Xtensa 8 Processor Features
- Highly efficient, small, ultra- low-power core with a 32-bit modern architecture and 5-stage pipeline
- Wide range of configurable options
- Local memories configurable up to 4MB with option for parity or ECC
- Extend with application-specific instructions, execution units and register files
- Use XPRES Compiler to automate customization for your C/C++ application code
- 32-bit wire input and 32-bit wire output GPIO port option for peripheral control and monitoring
- 2×32-bit queue FIFO interface option for data streaming directly to RTl or other Xtensa processors
- Optional floating point unit plus double-precision floating point acceleration
- Wide range of operating system support including Linux
- A complete software tool chain is automatically generated for each core
Designers using an Xtensa 8 DPU can select from an expanded library of pre-verified configuration options to get the exact functionality they need. Enhancements in this new generation processor include pairs of 32-bit GPIO (general purpose input/outputs) and 32-bit Queue interfaces for direct connection to RTL (register transfer level) blocks, and a low-area, double-precision floating point accelerator.
Because the Xtensa 8 processor core can be customized, designers have a wide range of choices available to meet area, power and performance requirements. Full synthesis scripts are provided for all major EDA vendors allowing designers to target their favorite libraries and processes. A typical small configuration (similar to Tensilica’s Diamond Standard 106Micro with an iterative 32×32 multiplier, separate instruction and data memory interfaces, an interrupt controller with 15 interrupts at two priority levels, an integrated timer, on-chip debugging hardware, and embedded trace support) consumes just 17 µW/MHz of power while occupying a mere 0.046mm squared in TSMC 40LP process technology. That same configuration, synthesized for maximum performance in the same process technology, can run up to 540 MHz and still only consumes 25 µW/MHz of power with an area of 0.074mm squared.
The Xtensa 8 processor core can be customized with new configuration check-box options that provide control and data input/output capabilities that entirely bypass the main system bus. This allows direct connectivity to blocks of RTL in the SOC, providing fine-grained, low-latency control of those hardware blocks. These connections also allow Xtensa 8 DPUs to stream data to RTL blocks at much higher speeds to dramatically improve system performance.
The 32-bit GPIO (general-purpose input output) interface provides 32 bits of input and 32 bits of output control and status information exchange that are naturally accessed directly as registers from the processor’s regular instruction set. This interface is ideal for peripheral control and monitoring.
The 32-bit input and 32-bit output Queue interfaces operate like FIFO (first in, first out) interfaces, providing a high-bandwidth and low latency mechanism for streaming data to and from other blocks in the system or other Xtensa processors. To the programmer’s viewpoint, input and output queue data is register based for simple and quick access — there is no need to load or store the data before and after any computation.
More info: Tensilica