The new ZeBu-Server comes standard with a powerful debug environment. ZeBu-Server features a wide array of tools that enables debugging at multiple levels of abstraction, because debugging a complex failure in a system-on-chip (SoC) design requires deterministically re-executing billions of clock cycles repeatedly until the problem is identified. ZeBu-Server is a scalable emulation system capable of handling up to one-billion application specific integrated circuit (ASIC) gates.
The ZeBu Smart Debug technology and methodology makes the most effective use of those cycles, allowing “debug convergence” as quickly as possible. Its debug features include three types of probes (static, flexible and dynamic) and static and dynamic triggers on sequential and combinational signals. ZeBu-Server offers support for SystemVerliog Assertions (SVAs), monitors, and checkers implemented via dpi-based transactors, and save and restore capabilities.
A complete waveform generation of sequential and combinational signals at the register transfer level (RTL) is available, as well as interactive set/get, force/release all internal signals at run-time without requiring recompilation.
The debug technology, when paired with a “Smart Debug” methodology, enables easy identification of even the most complex corner-case bugs by quickly filtering billions of cycles of raw data into relevant debug information.
ZeBu-Server can be used for all SoC verification needs across the entire development cycle, from hardware verification, hardware/software integration to embedded software validation. ZeBu-Server is priced at less than a penny for large configurations.
More info: EVE