A Power Backbone for Architecture to RTL Power Efficient SoC Design
Bernard Murphy, Chief Technology Officer of Atrenta, will present a paper at ARM techcon3 (formerly ARM Developers Conference) from 10:00 to 10:45 am on Friday, October 23, 2009. The title of the paper is A Power Backbone for architecture to RTL power efficient SoC Design. Dr. Murphy’s paper describes a real-world implementation of such an RTL-based design flow.
Dr. Murphy will describe a power management design flow that Atrenta has jointly developed with a large semiconductor company. Called a “power backbone”, the flow provides a top-down environment to define, optimize and manage the implementation of advanced power management strategies for SoC design. Murphy’s paper will cover a complete methodology for IP power modeling, architectural power planning, capturing and propagating power intent forward to chip implementation. Chip level RTL power estimation, reduction and power intent verification will also be covered. Murphy will discuss how, through this flow, users can achieve substantial power efficiencies in their SoC design.
Semiconductor and EDA (electronic design automation) authorities, analysts and pundits have recognized power optimization and management in current and future SoC (system-on-chip) design as the most crucial requirement for successful chip design and manufacture. These authorities also acknowledge that current gate-level chip design flows are nearing the end of their useful lives for the most advanced SoCs, and that RTL (register-transfer-level)-based design flows must come online to handle the newest crucial chip design, analysis, verification and signoff tasks.
More info: Atrenta
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