Synopsys Synphony High Level Synthesis

Synopsys launched Synphony High Level Synthesis (HLS) solution. Synphony HLS integrates M-language and model-based synthesis to deliver up to 10X higher design and verification productivity than traditional RTL flows for communications and multimedia applications. Synphony HLS creates optimized RTL for ASIC and FPGA implementation, architecture exploration, and rapid prototyping. Synphony HLS includes M-synthesis technology, C-model generation, HLS high level IP model library, and HLS engine for ASIC and FPGA. Synphony HLS is now in limited customer availability with general availability by the end of calendar year 2009.

Synopsys Synphony HLS (High Level Synthesis) solution

Synphony HLS complements C/C++-based flows by generating C-models for system validation and early software development in virtual platforms. Synphony HLS integrates with Synopsys’ Design Compiler, Synplify Premier, Confirma(TM), VCS, System Studio and Innovator products to deliver the most comprehensive prototyping, implementation and verification flows from algorithm to silicon.

Synopsys Synphony High Level Synthesis Features

  • M-Language Synthesis
    • Simpler, easier way to create a working algorithm
    • 50-100x smaller code than RTL
    • Fewer bugs introduced into flow
  • Automated Fixed-point Conversion Tools
    • Fast conversion of floating point M-code into fixed-point
    • Rapid exploration and refinement of precision
    • Eliminates recoding and re-verification into fixed-point models
  • Synthesizable Fixed-point High Level IP Model Library
    • Eliminates writing of fixed-point models from scratch
    • Faster verification at higher levels of abstraction
    • Offers more control over results
  • High Level Synthesis Optimizations and Transformations
    • Automatic system-wide pipeline insertion scheduling and resource sharing
    • IP-aware micro architecture optimization
    • Automatic loop unrolling, scheduling and pipelining
    • Target-aware optimization for FPGAs and ASICs
  • Integrated ASIC Flow
    • Automatic generation of RTL constraints and scripts for Design Complier
    • Advanced timing estimation using Design Compiler
    • Rapid architecture exploration of speed, area and power tradeoffs
  • Integrated FPGA Flow
    • Automatic generation of RTL constraints and scripts for Synplify Pro / Synplify Premier
    • Advanced timing estimation using Synplify Pro / Synplify Premier
    • Optimized resource mapping to advanced FPGA devices such as hardware multipliers, MACS, adders, memories and shift registers
    • Enables Rapid Prototyping
  • RTL Testbench Generation
    • Automatic generation of text vectors and scripts for RTL verification in VCS
  • C-Model Generation for Software Development and System Validation
    • Fast model creation for C-based verification
    • Begin software development earlier using virtual prototypes

More info: Synopsys