CEVA is offering a webinar on October 14, 2009 at 8 am Pacific time (11 am Eastern). The title of the webcast is Designing Low-power SoCs for Multimedia and Baseband. The online event will cover the main challenges involved with designing advanced SoCs while maintaining low-power. The CEVA webinar will provide insights into how SoC architects and designers can build state-of-the art SoCs for low power using different techniques and processor architectures.
Designing Low-power SoCs for Multimedia and Baseband Topics
- Future challenges in low power SoC design
- Key concepts in building an advanced processor architecture for low power
- Current trends and techniques used in low power processor architectures
- Implementation and verification flow of processors designed to meet low power
The webcast is ideal for SoC architects, designers, and system engineers who plan to implement SoCs with strict power constrains such as chips targeting battery powered devices.
To meet the relentless demand for improved feature sets and functionality in today’s advanced cellular baseband and multimedia chips, modern SoCs require more powerful processing capabilities than ever before. In the same breadth, these SoCs are expected to operate within the same power budget allocated to preceding, less complex chipsets, particularly for mobile applications. The CEVA webinar will deliver a fresh perspective on the main challenges involved in designing an advanced SoC while maintaining low-power consumption. It will provide insights into how SoC architects and designers can build state-of-the art SoCs for low power requirements using different techniques and processor architectures.
- Ran Snir – VLSI Department Manager, CEVA
- Eyal Bergman – Director of Product Marketing, CEVA