Cadence Improves TLM-Driven Design, Verification for Embedded Development

Cadence Design Systems has integrated their transaction-level model (TLM)-driven design and verification solution with industry-standard embedded software environments. The Cadence Incisive Enterprise Simulator (IES) and Incisive Software Extensions (ISX) TLM verification solutions now support Open Verification Methodology (OVM)-based TLM hardware/software co-verification, unified TLM and C/C++ hardware/software co-debugging, plus embedded software symbolic debug support for C/C++ compilers from ARM, GNU, Green Hills Software and ARC (now part of Virage Logic).

The extensions enable software developers to verify and debug their software earlier in the project and reduce time to market for the combined software and hardware product.

The Incisive TLM debugging capabilities provide an embedded software-oriented look-and-feel and automated probing of TLM transactions. ISX offers embedded software thread tracing that supports leading embedded software compilers, along with multiple abstraction levels from RTL to TLM. In addition, ISX automatically creates OVM test bench templates from embedded software sources to simplify hardware/software co-verification.

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