X-FAB TheKit Process Design Kits for Cadence Virtuoso IC 6.1

X-FAB Silicon Foundries introduced TheKit process design kits (PDK). TheKit is based on the Cadence Design Systems Virtuoso IC 6.1 custom design platform and SKILL programming language. TheKit is available for all of X-FAB’s process technologies from 1.0 um down to 0.18 um. The process design kit offers a smooth and easy migration from existing projects developed with Virtuoso IC 5.1 to Virtuoso IC 6.1. The automatic project setup, libraries, and default tool settings result in a seamless design flow that saves setup time.

TheKit was developed for the latest release of the Cadence Virtuoso custom design platform, IC 6.1. TheKit helps engineers reduce design time and ensures manufacturing-robust designs. TheKit (with the help of the SKILL language) supports advanced interactive and automated technologies, such as Cadence Virtuoso Analog Design Environment XL/GXL, for a fast and accurate verification and yield optimization.

X-FAB uses the Virtuoso AMS Designer as a simulation hub to link advanced analog and digital simulation engines into a seamless mixed-signal verification environment. For a full automated routing of custom ICs at any level of the design hierarchy, X-FAB supports Virtuoso routing technologies. To ensure a successful production tape-out and to make use of a solution that offers competitive single-processor and distributed processor performance during physical verification, X-FAB relies on the Cadence Physical Verification System.

X-FAB offers several digital libraries in the Cadence environment optimized for low power, low noise, high density and timing to allow customers to select the most appropriate devices for their specific applications. A large portfolio of analog libraries (e.g., DAC, ADC, OpAmps, Bandgaps, Oscillators), embedded non-volatile memory (NVM) IP such as eFlash, EEPROM and NV latches is available for X-FAB’s technology platforms. Two important design aspects are electrostatic discharge (ESD) robustness and Safe Operating Area (SOA) check. To address the first aspect, X-FAB provides a special tool called ESD-Design-Checker to identify possible ESD weaknesses on schematic level and to estimate the ESD robustness that can be expected for the design. For SOA checks, X-FAB provides additional SPICE models to check whether all primitive devices are operating within permitted ranges.

X-FAB also leverages the new Incremental Technology Database (ITDB), based on Open Access, which is a technology library enabling CAD group/users to add or modify technology parameters without violating the original foundry design rules. It simplifies the data management and requires less disk space, especially for processes that have many derivatives. The main foundry technology library is referenced and individual constraints can be overridden if they do not violate the basic minimum rules in the ITDB.

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