Synopsys DesignWare DDR3/2 PHY and digital controller IP now supports the emerging 1866 and 2133 Megabits per second (Mbps) data rates currently being added to the JEDEC DDR3 standard. The DDR3/2 PHY also supports the Low Voltage DDR3L specification that runs at 1.35V, making the DesignWare IP ideal for power-conscious designs where the change from 1.5V DDR3 to 1.35V DDR3L can reduce DRAM power consumption by up to 20%. The DesignWare DDR3/2 PHY supporting 2133 Mbps and 1.35V DDR3L is available now. The DesignWare DDR3/2 controllers supporting 2133 Mbps and 1.35V DDR3L are expected to be available in October 2009.
To support the full range of DDR3 data rates, the DesignWare DDR3/2 IP includes a unique PHY Utility Block with built-in data training circuits to enable in-system calibration, providing optimized system-level timing. As part of the data training sequence, the DDR3/2 IP includes the ability to remove bit-to-bit timing skew that can occur on the chip, in the package or on the circuit board. Removing the timing skew is necessary to achieve reliable system-level performance at data rates above 1066Mbps.
The DesignWare DDR3/2 PHY provides designers with a choice of interfaces to the memory controller IP. For the lowest latency interface, designers can utilize the complementary DesignWare DDR3/2 Memory Controller or Protocol Controller IP. Support for internally developed controllers is offered via an optional DFI2.1 compliant interface on the DDR3/2 PHY that provides designers with a common interface to ease the integration effort between the controller and PHY.
By providing early access to DDR3 IP that supports both 2133Mbps and 1.35V operation, Synopsys enables designers to implement higher performance or lower power DDR3 interfaces today.
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