Synfora has acquired Esterel Studio tool suite from Esterel EDA Technologies. Esterel Studio is based on the Esterel synchronous programming language in use for the design of control logic and bus systems by three of the top 10 semiconductor companies in system-on-chip (SoC) designs. Esterel Studio is complementary to the PICO algorithmic synthesis platform. The PICO Algorithmic Synthesis Platform provides productivity gains by creating application accelerators from an untimed C algorithm at the highest level of abstraction.
Esterel Studio is used primarily to design control-intensive silicon intellectual property (IP) blocks and complex reactive systems such as control circuits, embedded systems, human-machine interface, and communication protocols. Companies such as STMicroelectronics, Texas Instruments, NXP and Intel have used the Esterel programming language for more than 50 production designs.
Esterel Studio supports a complete flow from design to verification and supports textual or graphical design of large state machines with arbitrary embedded data path, animated simulation, and debugging. Esterel studio is able to generate either HDL (Verilog, VHDL) code or C / SystemC models from the same source code, which ensures that the models used in virtual platforms for software validation agree with the final hardware design. Esterel Studio also supports formal verification of the produced results, a critical capability for complex control-oriented designs.
In conjunction with the PICO platform, this will provide designers with an integrated design environment for the development of both control-intensive and algorithmic-intensive blocks. PICO yields quality of results (QoR) that is competitive with manual design by using a unique parallelizing compiler and multi-level hierarchical abstraction and IP reuse. It offers the highest possible level of abstraction for large designs and has been proven to provide huge productivity gains on the largest production designs, not just on small blocks.
More info: Synfora