TimingDesigner 9.2 Interfaces with Cadence Allegro PCB Signal Integrity

EMA Design Automation introduced EMA TimingDesigner 9.2, which interfaces with the Cadence Allegro PCB Signal Integrity (SI) technology. The TimingDesigner integration with Allegro PCB SI enables designers to do a full signal integrity and timing analysis early in the design phase, with best in class timing reporting technology to quickly and accurately manage timing paths. Engineers can then move their boards to manufacturing with the confidence that the design will operate as expected. EMA TimingDesigner 9.2 will be available late August with pricing starting at $2,640 for a 1 year license.

The TimingDesigner graphical interface makes developing and performing analysis on complex timing relationships easy, while enabling review of the entire signal path. Timing can be analyzed across traditional design domains (chip, package, board) allowing timing optimization at the system level. In addition, TimingDesigner 9.2 includes many new features and enhancements. For ASIC and FPGA designers, the new version includes enhanced support for SDC generation, 65nm and below support for Altera FPGAs, and a new interface to the Actel Libero development environment.

More info: EMA Design Automation TimingDesigner