DVCon 2010 Call for Papers, Panels, and Tutorials
The 2010 Design and Verification Conference (DVCon) has issued a call for paper, panel, and tutorial submissions. Presentations are highly technical in nature and reflect real life experiences in using various languages and tools. The conference for the functional design and verification of electronic systems focuses on the use of specialized design and verification languages. DVCon 2010 will be held February 23-25 at the DoubleTree Hotel in San Jose, California.
DVCon is seeking papers and panels that bring to life the complexity of verification, the real challenges designers face, and the latest practical and academic solutions. DVCon 2010 will highlight how the latest industrial and academic innovations can be effectively deployed in real projects. Of special interest will be activities that involve close cooperation between multiple vendors and a diverse user community, as demonstrated by the various open source software offerings and industry standards.
DVCon Topics of Interest
- Experiences using the latest verification methodologies
- System-level design and verification
- Mixed-signal and low power challenges
- Experiences in verification process and resource management
Paper and panel proposals are due September 14, 2009. Paper proposals should be submitted online. Email panel proposals to Stan Krolikoski at stanleyk@cadence.com.
Special session tutorial proposals are due October 5, 2009. A limited number of sponsored special session tutorials are available. Submit all proposals to Kathy Embler at kathy@mpassociates.com.
DVCon is sponsored by Accellera, which is an industry consortium dedicated to the development and standardization of design and verification languages.
More info: DVCon
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