Mentor Graphics Verification Academy

Mentor Graphics introduced the Verification Academy. The goals of the online academy are to provide the skills necessary to mature an organization’s advanced functional verification process capabilities. The Verification Academy provides a methodological bridge between high-level value propositions (related to advanced verification technology) and the low-level details (related to specific tool and verification language details). The Verification Academy provides informative presentations on advanced verification techniques.

Verification Academy Courses

Evolving Capabilities Module
Ensuring functional correctness on RTL designs continues to pose one of the greatest challenges for today’s ASIC, FPGA and SoC design teams. This module provides a common framework for all advanced functional verification modules contained within the Verification Academy. A simple evolving capabilities model is presented, which can be used as a tool for assessing an organization’s functional verification process capabilities.

Assertion-Based Verification Module
The design effort for complex ASICs has been able to scale linearly by increasing design reuse and adopting a well-architected, platform-based design structure. Unfortunately, functional verification has not benefited directly from this approach. This module explores one way to address increased design complexity to supplement traditional functional verification methods with assertion-based verification (ABV). Today, ABV has been successfully applied at multiple levels of design and verification abstraction — ranging from high-level assertions within transaction-level test benches down to implementation-level assertions synthesized into emulation and hardware.

Clock-Domain Crossing (CDC) Verification Module
For the past dozen or so years, static timing analysis has served the industry well by ensuring that all synchronous design blocks will not violate any of the design’s setup and hold-timing constraints. However, with the convergence of multiple applications into a complex SoC (such as digital-audio, video, wireless, and networking), as well as the industry’s adoption of an IP reuse strategy, project teams are now faced with a new set of clocking verification challenges that are not addressed by static timing analysis. This module introduces clock-domain crossing concepts and provides insight into understanding the challenges encountered in complex SoCs.

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