Cadence Design Systems achieved first-silicon results on 32-nanometer (nm) Common Platform high-k metal-gate (HKMG) technology manufactured at IBM. Cadence and the Common Platform alliance (consisting of IBM, Chartered Semiconductor Manufacturing, and Samsung Electronics) teamed to tackle systematic and random variability in advanced node designs. The silicon results represent a milestone for designers with stringent design-for-manufacturing (DFM) requirements, and can enable Encounter Digital Implementation (EDI) System to provide power savings, yield enhancement and time-to-market advantages.
The 32nm silicon results provide a rich and expansive data set modeling the HKMG process in relation to layout rules, design rule checking and device interconnect models. In addition, they capture critical information related to device and interconnect variability, including systematic, random, within-die and die-to-die variation, as well as manufacturing effects including lithography, thermal, stress, proximity effects, and copper deposition. Using this manufacturing intelligence during the physical design process, the Cadence Encounter Digital Implementation System can enable early and silicon-accurate DFM and variability modeling, characterization and optimization to provide a complete end-to-end flow.
The EDI System contains a full suite of DFM and statistical technologies that can be applied across the physical implementation flow. Manufacturing and yield can be addressed concurrently with timing, signal integrity, power, and area optimizations to ensure all aspects are addressed holistically before final tapeout. By modeling and optimizing for variability early in the design stage, designers reduce overall turnaround time and improve confidence that the chip will work as intended. Once these technologies are validated on 32/28nm technology, there is a potential to increase design predictability, resulting in higher-quality silicon with better time to volume.
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