Mentor Graphics Vista Supports Abstraction at Transaction Level
The Mentor Graphics Vista platform for comprehensive architecture design and prototyping now allows users to model, analyze, and optimize power at the transaction level of abstraction. The Vista platform enables engineers to model power at the transaction architecture level using advanced power estimation policies long before an implementation becomes available, or annotate more accurate power behavior based on attributes of the technology process of the target implementation IP blocks. The Vista platform is available for deployment with prices starting at $100K.
The Mentor Vista platform of low-power electronic system level (ESL) design tools provides a layered behavioral, timing, and power modeling design methodology coupled with the SystemC Transaction-level Modeling Standard (TLM-2.0) supported by the Open SystemC Initiative (OSCI). Vista offers an advanced design platform that allows chip designers and system architects to make viable decisions on hardware/software partitioning and architecture structures. With its advanced debug and analysis toolset, users can verify system-wide functionality, analyze and optimize systems under realistic traffic loads, and adjust system resources for optimal performance and power. Users can also explore various voltage scaling and shutdown techniques and apply the most efficient power management strategies.
Designers can ensure a cost-effective architecture with a suitable bandwidth that can carry the target application. Given the abstraction and fast simulation of the hardware representation, a model of the system can then be used as a virtual platform for early software development, analysis and validation, including the ability to profile power while executing application software.
If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.