Calypto Design Systems unveiled a fully automated design flow for advancing the delivery of optimized, high-performance IP blocks for SoC designs. The Sequential Optimization Flow features Calypto’s SLEC RTL tool and new analysis capabilities of the PowerPro CG (clock gating) tool. With Calypto’s Sequential Optimization Flow, designers can use a fully automated flow to optimize power, area, and timing for high-performance IP blocks, such as microprocessors and digital signal processors (DSPs). Engineers are also assured that functionality is maintained throughout the process.
The Calypto Sequential Optimization Flow includes PowerPro CG, which takes an RTL design and automatically generates a power-optimized RTL design. Both the original and power-optimized RTL designs are run through a third-party synthesis tool, such as the Cadence Encounter RTL Compiler to create two gate-level netlists. With the new automated analysis capabilities of PowerPro CG, the timing and power consumption of both netlists are automatically analyzed so that targeted retiming synthesis can be run on the power-optimized, gate-level netlist.
Using Calypto’s SLEC RTL, functional equivalence between the original RTL and the new timing- and power-optimized gate level netlist is verified. By combining gate-level retiming with automated RTL power optimization and sequential logic equivalence checking, Calypto’s Sequential Optimization Flow enables SoC design teams to optimize power, area, and timing for IP blocks and complex functions that were previously considered off-limits to such optimizations.
Calypto’s PowerPro CG runs on PC platforms running Linux and is priced at $295,000 (U.S.) for a one-year, time-based license. Existing PowerPro CG customers will be upgraded to the new version at no charge. SLEC RTL is available now and is priced at $175,000 (U.S.) for a one-year, time-based license. Synthesis solutions are available directly from their manufacturers.
More info: Calypto