ATopTech launched the Apogee hierarchical physical design solution. Apogee seamlessly integrates all the critical hierarchical design functions with a block-level implementation tool in a single environment. The Apogee top-level design tool is available now for adding to the Aprisa solution, which enables designers to perform the hierarchical place-and-route tasks as easily as running a flat place-and-route task. US pricing starts at $250,000.
Apogee includes the two key functions in hierarchical design: (1) top-down chip planning and partitioning and (2) bottom-up chip assembly and chip-level timing closure. These functions of Apogee are tightly integrated with Aprisa, so developers can easily manage hierarchical data and also switch between top-level design and block-level design seamlessly.
For top-down chip planning and partition, Apogee utilizes the place-and-route engines from Aprisa to achieve a high-quality partition generation, pin assignment, and feed-through insertion, helping designers create hierarchical designs with much better quality and unprecedented speed.
For bottom-up chip assembly and closure, Apogee makes it possible for developers to do full-chip timing analysis with automatically generated timing-accurate models for the blocks, with very fast run times. Apogee also helps designers work on individual blocks with the full-chip timing picture and fix the top-level timing issues.
More info: ATopTech