Synopsys Galaxy Constraint Analyzer improves designer productivity through look-ahead constraint analysis technology tuned for the Synopsys Galaxy Implementation Platform. The Galaxy Constraint Analyzer is an intuitive tool that enables designers to quickly assess the correctness and consistency of timing constraints. Correctness and consistency lead to more efficient runtimes in Synopsys’ Design Compiler synthesis and IC Compiler physical implementation tools. The Galaxy Constraint Analyzer features unique constraint debug capabilities to help designers eliminate long “trial-and-error iterations” during implementation, reducing design cost as a result of more predictable schedules all the way to full-chip signoff.
Galaxy Constraint Analyzer offers an extensive set of rule checks designed to maximize the efficiency of Design Compiler synthesis and IC Compiler physical implementation. In addition, Galaxy Constraint Analyzer uses technology based on Synopsys’ golden PrimeTime timing engine to ensure correct interpretation and propagation of constraints. This results in a signoff-correlated view of the constraints ahead of each step of the design implementation process. Galaxy Constraint Analyzer’s ability to deliver comprehensive constraint analysis on 10-million-gate designs in a matter of minutes, combined with a unique set of interactive analysis and debug capabilities, helps designers quickly identify and fix constraint issues within hours versus days.
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