Mentor Graphics Expanded Solution for TSMC Reference Flow 10.0

Mentor Graphics has expanded their set of tools and technologies included in the TSMC Reference Flow 10.0. The expanded Mentor track supports advanced functional verification for complex ICs, netlist-to-GDSII implementation for 28nm ICs, tighter integration with the ubiquitous Calibre physical verification and DFM platform, and tools for layout aware test failure diagnosis. The improved Mentor track also addresses low power design with Mentor tools for functional verification, IC implementation, and IC testing.

New Olympus-SoC IC Implementation Features

  • Advanced stage-based OCV analysis and optimization
    Setting different stage-based OCV values helps reduce pessimism and enables faster design closure
  • N28 routing rules
    Provides 28nm support for the complete netlist-to-GDSII flow, including support for the 28nm transparent half-node
  • Disjoint power domain
    Supports multiple floor plans in the same voltage domain to minimize congestion and reduce the need for hierarchy changes
  • UPF hierarchical low power automation
    Provides both top-down and bottom-up support for UPF-based, low-power designs giving designers greater flexibility

New Olympus-SoC and Calibre Design-for-Manufacturing Features

  • Litho hotspot fixing
    Improves yield by enabling the Olympus-SoC place-and-route tool to automatically fix litho hotspots detected by the Calibre LFD tool
  • Quick convergence of DMx fill for timing and ECOs
    The Olympus-SoC system invokes the Calibre CMPAnalyzer tool (which works with TSMC’s VCMP simulator) to analyze thickness variation for its impact on timing. The Olympus-SoC tool also supports hierarchical, incremental and timing-driven metal fill flows, significantly improving yield and reducing pessimism.
  • Cell-index-aware placement
    Reduces congestion and speeds routing by allotting more room for cells with difficult pin access
  • Electrical DFM
    The Calibre xRC and Calibre CMPAnalyzer products are integrated to allow simulated thickness information to be incorporated into parasitic extraction results to drive accurate circuit simulation. This also provides a solution for more efficient corner simulation and statistical analysis by providing statistical parasitic information to the Mentor Eldo circuit simulator.

New TestKompress and YieldAssist Reference Flow 10.0 Features

  • Embedded multiple detect ATPG
    Increases bridge fault detection without any increase in pattern size or test time
  • Layout aware diagnosis
    Eliminates false bridge/open suspects, enhances diagnosis resolution, and builds a foundation for effective yield analysis
  • Low-power ATPG
    Reduces power during all phases of scan test utilizing a constant-fill decompressor and power-aware control of existing clock gates

New Questa and 0-In functional Verification Features

  • Standards-based solution featuring support for IEEE Std. 1801-2009 UPF and IEEE Std. 1800-2005 SystemVerilog
  • Integrated low-power simulation and formal capabilities that verify advanced power management circuitry early in the design flow
  • Static and dynamic verification of complex clock domain crossing circuits to ensure proper operation in standard and low power modes

More info: Mentor Graphics