Synopsys announced In-Design Rail Analysis for accelerating design closure. In-Design Rail Analysis utilizes embedded PrimeRail analysis and fixing guidance technology to enable designers to easily perform power network verification throughout physical implementation. By identifying and fixing voltage-drop and electromigration issues earlier in the flow, designers can eliminate costly iterations late in the design process. Working in concert with IC Compiler’s Power Network Synthesis (PNS) and In-Design Physical Verification capabilities, In-Design Rail Analysis provides designers with a comprehensive solution for both the implementation and verification of power networks.
By eliminating complicated data exchanges and with no new tools to learn, In-Design Rail Analysis helps IC Compiler users ensure the integrity of their power network early and frequently during the physical implementation process, avoiding late-stage surprises close to tapeout. In-Design Rail Analysis works in tandem with IC Compiler’s PNS capability to enable designers to efficiently implement, optimize and refine power networks, significantly reducing overdesign. In addition, In-Design Physical Verification helps ensure that power networks are design-rule clean as refinements and fixes are implemented.
More info: Synopsys