2009 Embedded Systems Conference India

The Embedded Systems Conference India 2009 will take place July 22-24, 2009 at NIMHANS Convention Center, Hosur Road, Bangalore. The embedded technical conference offers engineers access to classes that delivers real-world solutions by leading industry experts. Attendees will meet and learn from experts in the embedded system universe. The conference value proposition is to provide answers to the engineer’s design challenges as well as upgrading their design skills.

FPGA Design Introduction
This class provides an overview of FPGA technology, manufacturers, tools and references. The class focuses on available FPGA component architectural features and trends for clock blocks, DSP blocks, embedded memories, hard IP functions, and interfaces including MACs, PHYs, transceivers and external memory interconnection. Programming, configuration, package and device selection, design capture, synthesis, implementation, simulation, testing, debug and verification are also addressed.

Plug and Play Protocols on CAN
The course covers basic CAN communication, evolution and current standards. Some of the messaging protocols will be discussed in detail along with their application areas. It brings out the need to evolve the CAN protocols to a new level and present a possible candidate for plug and play CAN application protocol.

Memory Partitioning – Why Change from a Flat Memory Model?
The course shows how to balance between memory cost and the security, safety and flexibility brought by modern Memory models.

FPGA Design Process and Best Practices
The initial phase of an FPGA design is focused on functional design implementation. Design tasks include requirement definition, system architecting, documentation, implementation decisions, design capture, board layout, behavioral simulation, synthesis, place and route and in-circuit configuration. This class is focused on efficient process implementation, common mistakes, oversights and best practices.

ARM Architecture and Efficient System Software Programming
Knowledge on ARM architecture. Knowledge on how to write and optimize the software running on ARM.

Inheritance, MI, and Thunks in C++
Covers the reasoning for using inheritance (Concrete, ABCs, Interfaces) and the correctness behind inheritance usage (LSP). It then goes on to examine the problems associated with Multiple Inheritance (MI), the unwanted side-effects (deadly diamond) and the unavoidable side-effects (thunks). It finishes off by exploring an alternative to MI by using UML style ports.

FPGA Design Optimization
FPGA optimization can be a difficult and challenging design phase. Optimization is the process of achieving higher levels of performance by refining functionality while potentially consuming fewer resources and less power. Optimization tasks include timing analysis and simulation, in-circuit debug, and in-circuit performance and power validation. Tool and device architecture knowledge are essential to effective design optimization. Key design optimization options include area and timing constraints, tool options, switches and modes. This class will discuss prioritized design optimization strategies and approaches.

Tasks, Threads, and Processes
The papers explores the often confusing and misused terms associated with concurrent and quasi-concurrent programming, namely Task, Thread and Process. It looks at the history of these terms, where their influences came from, and how they are inconsistently used in modern times. It explores how the hardware architecture can also have a bearing on the use of these terms to describe concurrent programming. It also looks at the influence of certain programming languages, from Ada to Java, on how threading is managed within a programming environment.

HDL Design Options
There are a broad range of available programmable logic design capture languages and tools. This class will review the Hardware Description Language (HDL) options and their respective advantages and applications. Languages targeting synthesized functionality including VHDL and Verilog will be discussed. Testbenching language options including SystemVerilog, Verilog and VHDL will also be reviewed. Emerging design capture options including model-based development and C-to-RTL will be addressed. HDL Design capture and management, best practices and common design challenges will be presented.

Techniques for Developing Embedded and Real-time systems
Embedded systems are involved in almost every facet of modern life. Modern automobiles may contain as many as 65 embedded microprocessors, controlling such tasks as anti-lock braking, climate control, engine control, audio system control, and airbag deployment. Modern cell phones integrate millions of lines of code, partitioned between several processors on a single device. The class presents practical lessons and techniques for use in designing, implementing, integrating, and testing software for modern embedded systems. The class describes what an embedded system is, what makes them different, and what designers need to know to develop embedded systems.

Embedded Hypervisors – Trends, Techniques, and Applications
How new hardware and software solutions enable safe and secure devices through embedded virtualization.

Single and Multi-core Processor Design within FPGAs
FPGAs provide a flexible platform for implementation of single and multi-core processor arrays with optimized co-processing elements. This class discusses optimizing data flow and processor core to peripheral interfaces, as well as multi-core interface, data coherency, and algorithm implementation management. An overview of available soft and hard FPGA processor options and peripheral blocks will also be presented. The class will provide an overview of the implementation of a soft processor core with custom peripherals and discuss scaling this architecture into a multi-processor array.

Inside the Bootloader of an Embedded System
This presentation addresses various aspects of the boot loader of an embedded system. It includes configuring processor modes; vector table initialisation; stack initialisation; execution from RAM/Flash; memory initialisation and tests; initialisation of various hardware devices; downloading the image from the communication channels; linker command file and placing code in internal and external RAM areas etc. It also addresses initialising the RTOS and initialising and starting the RTOS based application. It also addresses the various debugging techniques and instrumentation to be provided for field support.

Understanding Mutual Exclusion: Not All Mutexes are Created Equal
The majority of modern embedded software systems use concurrency in their programming model. Once concurrency is introduced the requirement of support for basic mutual exclusion for critical regions is essential. This paper explores the development of mutual exclusion principles, from Dykstras’ semaphores, to modern day mutexes. It looks at the basic requirements, the potential issues (e.g. deadlock) and how these issues are typically overcome. However, modern mutexes typically have the same API but differ significantly in there behaviour, including aspects such as priority inheritance and death detection. This can easily catch a programmer out when porting from one RTOS to another.

High Speed FPGA Design
FPGA interfaces are increasing in speed and complexity as designs increase in integration and performance. There are many factors to consider when implementing high-speed design interfaces with FPGAs including signal and power integrity, clock management, Simultaneously Switching Output (SSO) analysis, transceivers, MAC and PHY implementation and high performance memory interfaces (DDR2, DDR3). This class explores available design implementation and analysis tools, design debug, and suggested practices for avoiding interface and PCB design mistakes and oversights. High-speed serial protocols will be addressed.

Multicore Application Development, Configuration, Virtualization, Visualization
A multicore processor is an integrated circuit in which two or more processors have been attached for enhanced performance, reduced power consumption, and more efficient simultaneous processing of multiple tasks. But to get an application up and running on a MC device, there are three key focus areas for application developers. Configuration of the complex processing elements and accelerators is key to system performance. Virtualization of the underlying HW provides the necessary abstraction required for complex applications. Visualization of the MC processing elements, peripherals, and communication interconnect is key for system integration. We will review these three key areas and give examples of how to use these techniques to integrate a multicore application.

DSP Design within FPGAs
With increasing levels of DSP performance and functionality within processors and FPGAs design implementation tradeoffs are becoming more complex. Which algorithms and functions are well suited for implementation within FPGAs? This class provides an overview of the architectures, design flows and tools which support implementation of DSP functionality within FPGAs. Design implementation tradeoffs, data-flow management, performance optimization, tool complexity and integration are discussed. Filter theory, terminology, design architectures, and tool options are discussed.

Multi-core Processing, Application Development, Integration, and Debug
A multicore processor is an integrated circuit in which two or more processors have been attached for enhanced performance; reduced power consumption; and more efficient simultaneous processing of multiple tasks. In this course we will overview multicore terminology; discuss the advantages and disadvantages of multicore; as well as some of the multicore programming models such as SMP; AMP; and blending. We’ll look at the software impact of multicore processing including issues associated with partitioning; communication; agglomeration; and mapping. We will also take a look at some embedded multicore processors and embedded applications using multicore. We will also discuss benchmarking of multicore applications and how to determine if we are meeting our performance goals of the system.

Guidelines for Writing Efficient C/C++ Code – Part 1
With ineffective programming; even a perfect compiler can not generate efficient code. This talk will focus on the hows and whys of programming with today’s modern compilers and how to get good performance out of them. Examples will be given to illustrate how simple source code transformations can result in big savings regardless of the compiler used. The talk will cover choice of data types; variable scopes; the restrict keyword; floating point arithmetic; assembly statements; packing; loop optimizations; and volatile memory.

Efficient Prototyping Model for SoC Validation on Multi-FPGA Platform
Architecture and methodologies for Multi-FPGA prototyping of large ASIC design using: 1. Scalable inter-FPGA communication 2. A new partitioning scheme 3. Intrusive and non-intrusive debug tools 4. Efficient resource utilization strategies

Guidelines for Writing Efficient C/C++ Code – Part 2
With ineffective programming; even a perfect compiler can not generate efficient code. This talk will focus on the hows and whys of programming with today’s modern compilers and how to get good performance out of them. Examples will be given to illustrate how simple source code transformations can result in big savings regardless of the compiler used. The talk will cover choice of data types; variable scopes; the restrict keyword; floating point arithmetic; assembly statements; packing; loop optimizations; and volatile memory.

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