Synopsys introduced the DesignWare IP solution for PCI Express (PCIe) 3.0. The solution consists of digital controllers, PHY ,and verification IP. Synopsys’ DesignWare IP enables easy integration of the 8.0 GT/s PCI Express 3.0 interface into system-on-chips (SoCs) for high-performance enterprise computing applications. The DesignWare IP for PCI Express 3.0 helps designers to quickly incorporate the new PCI Express 3.0 features into their products with less risk and improved time to market. The DesignWare digital controllers and Verification IP for PCI Express 3.0 are available now for selected early adopters. The DesignWare PHYs for PCI Express 3.0 are currently in development for leading foundry processes.
Synopsys’ suite of digital controllers for PCI Express 3.0 is based on the DesignWare IP for PCI Express 2.0/1.1 architecture, allowing designers to benefit from small area and low latency to reduce costs and improve overall system throughput. The DesignWare digital controllers for PCI Express 3.0 implement the same interfaces as PCI Express 2.0, allowing customers to quickly upgrade to PCI Express 3.0.
For the physical layer, Synopsys is developing a PHY architecture specifically optimized for PCI Express 3.0 with high-performance margins to allow the PHY to achieve the final PCI Express 3.0 specifications in areas such as jitter, margin, and receive sensitivity. In addition, the advanced built-in diagnostic capabilities and ATE test vectors enable at-speed product testing of the DesignWare PHY IP for PCI Express 3.0 and on-chip visibility into the actual link performance.
Complementing the digital controllers and PHY is the DesignWare Verification IP for PCI Express 3.0, which supports directed testing and constrained random methodologies defined in the Verification Methodology Manual (VMM) for SystemVerilog and allows designers to create complex protocol test scenarios for verifying their SoCs.
PCI Express 3.0 is the next generation of the PCI Express I/O standard, which is currently under development within the PCI Special Interest Group (PCI-SIG) at a preliminary revision 0.5.